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FEATURES
Blackfin(R) Embedded Processor ADSP-BF531/ADSP-BF532/ADSP-BF533
External Memory Controller with glueless support for SDRAM, SRAM, FLASH, and ROM Flexible memory booting options from SPI and external memory
Up to 600 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit Shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring 0.8 V to 1.2 V core VDD with on-chip voltage regulation 3.3 V and 2.5 V tolerant I/O 160-ball mini-BGA, 169-ball lead free PBGA, and 176-lead LQFP packages
PERIPHERALS
Parallel Peripheral Interface (PPI)/GPIO, supporting ITU-R 656 video data formats Two dual-channel, full duplex synchronous serial ports, supporting eight stereo I2S channels 12-channel DMA controller SPI compatible port Three Timer/Counters with PWM support UART with support for IrDA(R) Event Handler Real-Time Clock Watchdog Timer Debug/JTAG interface On-chip PLL capable of 1x to 63x frequency multiplication Core Timer
MEMORY
Up to 148K bytes of on-chip memory: 16K bytes of instruction SRAM/Cache 64K bytes of instruction SRAM 32K bytes of data SRAM/Cache 32K bytes of data SRAM 4K bytes of scratchpad SRAM Two dual-channel memory DMA controllers Memory Management Unit providing memory protection
JTAG TEST AND EMULATION
EVENT CONTROLLER/ CORE TIMER
WATCHDOG TIMER
VOLTAGE REGULATOR
B
L1 INSTRUCTION MEMORY MMU L1 DATA MEMORY CORE / SYSTEM BUS INTERFACE
REAL-TIME CLOCK UART PORT IRDA(R)
TIMER0, TIMER1, TIMER2
PPI / GPIO
DMA CONTROLLER
SERIAL PORTS (2) SPI PORT
BOOT ROM EXTERNAL PORT FLASH, SDRAM CONTROL
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADSP-BF531/ADSP-BF532/ADSP-BF533
TABLE OF CONTENTS
General Description ................................................. 3 Portable Low Power Architecture ............................. 3 System Integration ................................................ 3 ADSP-BF531/2/3 Processor Peripherals ..................... 3 Blackfin Processor Core .......................................... 3 Memory Architecture ............................................ 4 DMA Controllers .................................................. 8 Real-Time Clock ................................................... 8 Watchdog Timer .................................................. 9 Timers ............................................................... 9 Serial Ports (SPORTs) ............................................ 9 Serial Peripheral Interface (SPI) Port ......................... 9 UART Port ........................................................ 10 Programmable Flags (PFx) .................................... 10 Parallel Peripheral Interface ................................... 10 Dynamic Power Management ................................ 11 Voltage Regulation .............................................. 12 Clock Signals ..................................................... 12 Booting Modes ................................................... 13 Instruction Set Description ................................... 14 Development Tools ............................................. 14 Designing an Emulator Compatible Processor Board ... 15 Pin Descriptions .................................................... 16 Specifications ........................................................ 19 Recommended Operating Conditions ...................... 19 Electrical Characteristics ....................................... 19 Absolute Maximum Ratings .................................. 20 ESD Sensitivity ................................................... 20 Timing Specifications ........................................... 21 Clock and Reset Timing ..................................... 22 Asynchronous Memory Read Cycle Timing ............ 23 Asynchronous Memory Write Cycle Timing ........... 24 SDRAM Interface Timing .................................. 25 External Port Bus Request and Grant Cycle Timing .. 26 Parallel Peripheral Interface Timing ...................... 27 Serial Ports ..................................................... 28 Serial Peripheral Interface (SPI) Port --Master Timing ........................................... 33 Serial Peripheral Interface (SPI) Port --Slave Timing ............................................. 34 Universal Asynchronous Receiver-Transmitter (UART) Port--Receive and Transmit Timing ...... 35 Programmable Flags Cycle Timing ....................... 36 Timer Cycle Timing .......................................... 37 JTAG Test And Emulation Port Timing ................. 38 Output Drive Currents ......................................... 39 Power Dissipation ............................................... 41 Test Conditions .................................................. 42 Environmental Conditions .................................... 45 160-Lead BGA Pinout ............................................. 46 169-Ball PBGA Pinout ............................................. 49 176-Lead LQFP Pinout ............................................ 51 Outline Dimensions ................................................ 53 Ordering Guide ..................................................... 56
REVISION HISTORY
Revision 0: Initial Version
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GENERAL DESCRIPTION
The ADSP-BF531/2/3 processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The ADSP-BF531/2/3 processors are completely code and pin compatible, differing only with respect to their performance and on-chip memory. Specific performance and memory configurations are shown in Table 1. Table 1. Processor Comparison
ADSP-BF531 400 MHz 800 MMACs 16K bytes 16K bytes 16K bytes ADSP-BF532 400 MHz 800 MMACs 16K bytes 32K bytes 32K bytes ADSP-BF533 600 MHz 1200 MMACs 16K bytes 64K bytes 32K bytes 32K bytes 4K bytes
ADSP-BF531/2/3 PROCESSOR PERIPHERALS
The ADSP-BF531/2/3 processor contains a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see the functional block diagram in Figure 1 on Page 1). The general-purpose peripherals include functions such as UART, Timers with PWM (Pulse-Width Modulation) and pulse measurement capability, general-purpose flag I/O pins, a Real-Time Clock, and a Watchdog Timer. This set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the part. In addition to these general-purpose peripherals, the ADSP-BF531/2/3 processor contains high speed serial and parallel ports for interfacing to a variety of audio, video, and modem codec functions; an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources; and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. All of the peripherals, except for general-purpose I/O, RealTime Clock, and timers, are supported by a flexible DMA structure. There is also a separate memory DMA channel dedicated to data transfers between the processor's various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. The ADSP-BF531/2/3 processor includes an on-chip voltage regulator in support of the ADSP-BF531/2/3 processor Dynamic Power Management capability. The voltage regulator provides a range of core voltage levels from a single 2.25 V to 3.6 V input. The voltage regulator can be bypassed at the user's discretion.
Maximum Performance Instruction SRAM/Cache Instruction SRAM Data SRAM/Cache Data SRAM Scratchpad
4K bytes
4K bytes
By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package.
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature Dynamic Power Management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This translates into longer battery life for portable appliances.
BLACKFIN PROCESSOR CORE
As shown in Figure 2 on Page 5, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register file. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields. Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported. The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives,
SYSTEM INTEGRATION
The ADSP-BF531/2/3 processors are highly integrated systemon-a-chip solutions for the next generation of digital communication and consumer multimedia applications. By combining industry-standard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The system peripherals include a UART port, an SPI port, two serial ports (SPORTs), four general-purpose timers (three with PWM capability), a real-time clock, a watchdog timer, and a Parallel Peripheral Interface.
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saturation and rounding, and sign/exponent detection. The set of video instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions. For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). By also using the second ALU, quad 16-bit operations are possible. The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit Index, Modify, Length, and Base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The Memory Management Unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The architecture provides three modes of operation: User mode, Supervisor mode, and Emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while Supervisor mode has unrestricted access to the system and core resources. The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The ADSP-BF531/2/3 processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip memory as cache or SRAM, and larger, lower cost and performance off-chip memory systems. See Figure 3 on Page 5, Figure 4 on Page 5, and Figure 5 on Page 6. The L1 memory system is the primary highest performance memory available to the Blackfin processor. The off-chip memory system, accessed through the External Bus Interface Unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical memory. The memory DMA controller provides high bandwidth datamovement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces.
Internal (On-Chip) Memory
The ADSP-BF531/2/3 processor has three blocks of on-chip memory providing high bandwidth access to the core. The first is the L1 instruction memory, consisting of up to 80K bytes SRAM, of which 16K bytes can be configured as a four-way set-associative cache. This memory is accessed at full processor speed. The second on-chip memory block is the L1 data memory, consisting of up to two banks of up to 32K bytes each. Each memory bank is configurable, offering both cache and SRAM functionality. This memory block is accessed at full processor speed. The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
The External Bus interface can be used with both asynchronous devices such as SRAM, FLASH, EEPROM, ROM, and I/O devices, and synchronous devices such as SDRAMs. The bus width is always 16 bits. A1 is the least significant address of a 16-bit word. 8-bit peripherals should be addressed as if they were 16-bit devices, where only the lower 8 bits of data should be used. The PC133-compliant SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. The SDRAM controller allows one row to be open for each internal SDRAM bank, for up to four internal SDRAM banks, improving overall system performance.
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ADDRE SS ARITHMETIC UNIT
SP FP P5 P4 P3 P2 P1 P0
I3 I2 I1 I0
L3 L2 L1 L0
B3 B2 B1 B0
M3 M2 M1 M0
DAG0
DAG 1
S EQUENCER
ALIG N
DECO DE LD0 32 BITS R7 R6 R5 R4 R3 R2 R1 R0 R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.L R0.L BARREL SHIFTER 40 40 16 8 8 8 16 8 CONTRO L UNIT
LOO P BUF FE R
LD1 32 BITS
SD 32 BI TS
A0
A1
DATA ARITHME TIC UNI T
Figure 2. Blackfin Processor Core
0xFFFF FFFF CORE MMR REGISTERS (2M BYTE) 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM (4K BYTE) RESERVED 0xFFA1 4000 INSTRUCTION SRAM / CACHE (16K BYTE) 0xFFA1 0000 INSTRUCTION SRAM (64K BYTE) 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK B SRAM / CACHE (16K BYTE) 0xFF90 4000 DATA BANK B SRAM (16K BYTE) 0xFF90 0000 RESERVED 0xFF80 8000 DATA BANK A SRAM / CACHE (16K BYTE) 0xFF80 4000 DATA BANK A SRAM (16K BYTE) 0xFF80 0000 RESERVED 0xEF00 0000 0x2040 0000 ASYNC MEMORY BANK 3 (1M BYTE) 0x2030 0000 ASYNC MEMORY BANK 2 (1M BYTE) 0x2020 0000 ASYNC MEMORY BANK 1 (1M BYTE) 0x2010 0000 ASYNC MEMORY BANK 0 (1M BYTE) 0x2000 0000 RESERVED 0x0800 0000 SDRAM MEMORY (16M BYTE TO 128M BYTE) 0x0000 0000
EXTERNAL MEMORY MAP INTERNAL MEMORY MAP
0xFFFF FFFF CORE MMR REGISTERS (2M BYTE) 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM (4K BYTE) RESERVED 0xFFA1 4000 INSTRUCTION SRAM / CACHE (16K BYTE) 0xFFA1 0000 INSTRUCTION SRAM (32K BYTE) 0xFFA0 8000 RESERVED 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK B SRAM / CACHE (16K BYTE) 0xFF90 4000 RESERVED 0xFF80 8000 DATA BANK A SRAM / CACHE (16K BYTE) 0xFF80 4000 RESERVED 0xEF00 0000 0x2040 0000 ASYNC MEMORY BANK 3 (1M BYTE) 0x2030 0000 ASYNC MEMORY BANK 2 (1M BYTE) 0x2020 0000 ASYNC MEMORY BANK 1 (1M BYTE) 0x2010 0000 ASYNC MEMORY BANK 0 (1M BYTE) 0x2000 0000 RESERVED 0x0800 0000 SDRAM MEMORY (16M BYTE TO 128M BYTE) 0x0000 0000
EXTERNAL MEMORY MAP INTERNAL MEMORY MAP
0xFFB0 0000
0xFFB0 0000
RESERVED
RESERVED
Figure 3. ADSP-BF533 Internal/External Memory Map
Figure 4. ADSP-BF532 Internal/External Memory Map
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Event Handling
0xFFFF FFFF CORE MMR REGISTERS (2M BYTE) 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM (4K BYTE) 0xFFB0 0000 RESERVED INSTRUCTION SRAM / CACHE (16K BYTE) 0xFFA1 0000 RESERVED 0xFFA0 C000 INSTRUCTION SRAM (16K BYTE) 0xFFA0 8000 RESERVED 0xFFA0 0000 RESERVED 0xFF90 8000 RESERVED 0xFF90 4000 RESERVED 0xFF80 8000 DATA BANK A SRAM / CACHE (16K BYTE) 0xFF80 4000 RESERVED 0xEF00 0000 0x2040 0000 ASYNC MEMORY BANK 3 (1M BYTE) 0x2030 0000 ASYNC MEMORY BANK 2 (1M BYTE) 0x2020 0000 ASYNC MEMORY BANK 1 (1M BYTE) 0x2010 0000 ASYNC MEMORY BANK 0 (1M BYTE) 0x2000 0000 RESERVED 0x0800 0000 SDRAM MEMORY (16M BYTE TO 128M BYTE) 0x0000 0000
EXTERNAL MEMORY MAP INTERNAL MEMORY MAP
0xFFA1 4000
The event controller on the ADSP-BF531/2/3 processor handles all asynchronous and synchronous events to the processor. The ADSP-BF531/2/3 processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller provides support for five different types of events: * Emulation - An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. * Reset - This event resets the processor. * Non-Maskable Interrupt (NMI) - The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system. * Exceptions - Events that occur synchronously to program flow (i.e., the exception will be taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. * Interrupts - Events that occur asynchronously to program flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The ADSP-BF531/2/3 processor Event Controller consists of two stages, the Core Event Controller (CEC) and the System Interrupt Controller (SIC). The Core Event Controller works with the System Interrupt Controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the generalpurpose interrupts of the CEC.
RESERVED
Figure 5. ADSP-BF531 Internal/External Memory Map
The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks will only be contiguous if each is fully populated with 1M byte of memory.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one of which contains the control MMRs for all core functions, and the other of which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15-7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest-priority interrupts (IVG15-14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF531/2/3 processor. Table 2 describes the inputs to the CEC, identifies their names in the Event Vector Table (EVT), and lists their priorities.
Booting
The ADSP-BF531/2/3 processor contains a small boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF531/2/3 processor is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Booting Modes on Page 13.
System Interrupt Controller (SIC)
The System Interrupt Controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF531/2/3 processor provides a default mapping, the user can alter the mappings and priorities of
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Table 2. Core Event Controller (CEC)
Priority (0 is Highest) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Event Class Emulation/Test Control Reset Non-Maskable Interrupt Exception Reserved Hardware Error Core Timer General Interrupt 7 General Interrupt 8 General Interrupt 9 General Interrupt 10 General Interrupt 11 General Interrupt 12 General Interrupt 13 General Interrupt 14 General Interrupt 15 EVT Entry EMU RST NMI EVX IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
Table 3. System Interrupt Controller (SIC)
Peripheral Interrupt Event PLL Wakeup DMA Error PPI Error SPORT 0 Error SPORT 1 Error SPI Error UART Error Real-Time Clock DMA Channel 0 (PPI) DMA Channel 1 (SPORT 0 RX) DMA Channel 2 (SPORT 0 TX) DMA Channel 3 (SPORT 1 RX) DMA Channel 4 (SPORT 1 TX) DMA Channel 5 (SPI) DMA Channel 6 (UART RX) DMA Channel 7 (UART TX) Timer 0 Timer 1 Timer 2 PF Interrupt A PF Interrupt B DMA Channels 8 and 9 (Memory DMA Stream 1) DMA Channels 10 and 11 (Memory DMA Stream 0) Software Watchdog Timer Default Mapping IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG11 IVG11 IVG11 IVG12 IVG12 IVG13 IVG13 IVG13
interrupt events by writing the appropriate values into the Interrupt Assignment Registers (IAR). Table 3 describes the inputs into the SIC and the default mappings into the CEC.
Event Control
The ADSP-BF531/2/3 processor provides the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide: * CEC Interrupt Latch Register (ILAT) - The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared. * CEC Interrupt Mask Register (IMASK) - The IMASK register controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.) * CEC Interrupt Pending Register (IPEND) - The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3 on Page 7. * SIC Interrupt Mask Register (SIC_IMASK)- This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in the register, that peripheral event is unmasked and will be processed by the system when asserted. A cleared bit in the register masks the peripheral event, preventing the processor from servicing the event. * SIC Interrupt Status Register (SIC_ISR) - As multiple peripherals can be mapped to a single event, this register allows the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event. * SIC Interrupt Wakeup Enable Register (SIC_IWR) - By enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. (For more information, see Dynamic Power Management on Page 11.)
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Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC will recognize and queue the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor. DMA transfers can be controlled by a very flexible descriptor based methodology or by a standard register based autobuffer mechanism.
REAL-TIME CLOCK
The ADSP-BF531/2/3 processor Real-Time Clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 KHz crystal external to the ADSP-BF531/2/3 processor. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low-power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. The 32.768 KHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and a 32,768-day counter. When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day. The stopwatch function counts down from a programmed value, with one-second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated. Like other peripherals, the RTC can wake up the processor from Sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the processor from Deep Sleep mode, and wake up the on-chip internal voltage regulator from a powered-down state. Connect RTC pins RTXI and RTXO with external components as shown in Figure 6.
RTXI R1 RTXO
DMA CONTROLLERS
The ADSP-BF531/2/3 processor has multiple, independent DMA controllers that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the ADSP-BF531/2/3 processor's internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMAcapable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the SPORTs, SPI port, UART, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel. The ADSP-BF531/2/3 processor DMA controller supports both 1-dimensional (1D) and 2-dimensional (2D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to 32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be de-interleaved on the fly. Examples of DMA types supported by the ADSP-BF531/2/3 processor DMA controller include: * A single, linear buffer that stops upon completion * A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer * 1-D or 2-D DMA using a linked list of descriptors * 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page In addition to the dedicated peripheral DMA channels, there are two memory DMA channels provided for transfers between the various memories of the ADSP-BF531/2/3 processor system. This enables transfers of blocks of data between any of the memories--including external SDRAM, ROM, SRAM, and flash memory--with minimal processor intervention. Memory
X1 C1 C2
SUGGESTED COMPONENTS: ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 12 PF LOAD (SURFACE-MOUNT PACKAGE) C1 = 22 PF C2 = 22 PF R1 = 10 M OHM NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.
Figure 6. External Components for RTC
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WATCHDOG TIMER
The ADSP-BF531/2/3 processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, non-maskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. If configured to generate a hardware reset, the watchdog timer resets both the core and the ADSP-BF531/2/3 processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. The timer is clocked by the system clock (SCLK), at a maximum frequency of fSCLK. * Clocking - Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. * Word length - Each SPORT supports serial data words from 3 to 32 bits in length, transferred most-significant-bit first or least-significant-bit first. * Framing - Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. * Companding in hardware - Each SPORT can perform A-law or -law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. * DMA operations with single-cycle overhead - Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory. * Interrupts - Each transmit and receive port generates an interrupt upon completing the transfer of a data-word or after transferring an entire data buffer or buffers through DMA. * Multichannel capability - Each SPORT supports 128 channels out of a 1024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards.
TIMERS
There are four general-purpose programmable timer units in the ADSP-BF531/2/3 processor. Three timers have an external pin that can be configured either as a Pulse-Width Modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse-widths and periods of external events. These timers can be synchronized to an external clock input to the PF1 pin, an external clock input to the PPI_CLK pin, or to the internal SCLK. The timer units can be used in conjunction with the UART to measure the width of the pulses in the data stream to provide an auto-baud detect function for a serial channel. The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system clock or to a count of external signals. In addition to the three general-purpose programmable timers, a fourth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
The ADSP-BF531/2/3 processor has an SPI-compatible port that enables the processor to communicate with multiple SPIcompatible devices. The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSI, and Master InputSlave Output, MISO) and a clock pin (Serial Clock, SCK). An SPI chip select input pin (SPISS) lets other SPI devices select the processor, and seven SPI chip select output pins (SPISEL7-1) let the processor select other SPI devices. The SPI select pins are reconfigured Programmable Flag pins. Using these pins, the SPI port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments. The SPI port's baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller, configurable to support transmit or receive data streams. The SPI's DMA controller can only service unidirectional accesses at any given time. The SPI port's clock rate is calculated as: f SCLK SPI Clock Rate = -------------------------------2 x SPI_Baud Where the 16-bit SPI_Baud register contains a value of 2 to 65,535.
SERIAL PORTS (SPORTS)
The ADSP-BF531/2/3 processor incorporates two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features: * I2S capable operation. * Bidirectional operation - Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I2S stereo audio. * Buffered (8-deep) transmit and receive ports - Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers.
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During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
PROGRAMMABLE FLAGS (PFX)
The ADSP-BF531/2/3 processor has 16 bidirectional, generalpurpose Programmable Flag (PF15-0) pins. Each programmable flag can be individually controlled by manipulation of the flag control, status and interrupt registers: * Flag Direction Control Register - Specifies the direction of each individual PFx pin as input or output. * Flag Control and Status Registers - The ADSP-BF531/2/3 processor employs a "write one to modify" mechanism that allows any combination of individual flags to be modified in a single instruction, without affecting the level of any other flags. Four control registers are provided. One register is written in order to set flag values, one register is written in order to clear flag values, one register is written in order to toggle flag values, and one register is written in order to specify a flag value. Reading the flag status register allows software to interrogate the sense of the flags. * Flag Interrupt Mask Registers - The two Flag Interrupt Mask Registers allow each individual PFx pin to function as an interrupt to the processor. Similar to the two Flag Control Registers that are used to set and clear individual flag values, one Flag Interrupt Mask Register sets bits to enable interrupt function, and the other Flag Interrupt Mask register clears bits to disable interrupt function. PFx pins defined as inputs can be configured to generate hardware interrupts, while output PFx pins can be triggered by software interrupts. * Flag Interrupt Sensitivity Registers - The two Flag Interrupt Sensitivity Registers specify whether individual PFx pins are level- or edge-sensitive and specify--if edge-sensitive--whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity.
UART PORT
The ADSP-BF531/2/3 processor provides a full-duplex Universal Asynchronous Receiver/Transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART port includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation: * PIO (Programmed I/O) - The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. * DMA (Direct Memory Access) - The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The UART port's baud rate, serial data format, error code generation and status, and interrupts are programmable: * Supporting bit rates ranging from (fSCLK/ 1,048,576) to (fSCLK/16) bits per second. * Supporting data formats from 7 to12 bits per frame. * Both transmit and receive operations can be configured to generate maskable interrupts to the processor. The UART port's clock rate is calculated as: f SCLK UART Clock Rate = ----------------------------------------------16 x UART_Divisor Where the 16-bit UART_Divisor comes from the DLH register (most significant 8 bits) and DLL register (least significant 8 bits). In conjunction with the general-purpose timer functions, autobaud detection is supported. The capabilities of the UART are further extended with support for the Infrared Data Association (IrDA(R)) Serial Infrared Physical Layer Link Specification (SIR) protocol.
PARALLEL PERIPHERAL INTERFACE
The processor provides a Parallel Peripheral Interface (PPI) that can connect directly to parallel A/D and D/A converters, ITU-R 601/656 video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock pin, up to 3 frame synchronization pins, and up to 16 data pins. The input clock supports parallel data rates up to half the system clock rate. In ITU-R 656 modes, the PPI receives and parses a data stream of 8-bit or 10-bit data elements. On-chip decode of embedded preamble control and synchronization information is supported. Three distinct ITU-R 656 modes are supported: * Active Video Only - The PPI does not read in any data between the End of Active Video (EAV) and Start of Active Video (SAV) preamble symbols, or any data present during
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the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI. * Vertical Blanking Only - The PPI only transfers Vertical Blanking Interval (VBI) data, as well as horizontal blanking information and control byte sequences on VBI lines. * Entire Field - The entire incoming bitstream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. Though not explicitly supported, ITU-R 656 output functionality can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and streaming the data out the PPI in a frame sync-less mode. The processor's 2D DMA features facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis. The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. The modes are divided into four main categories, each allowing up to 16 bits of data transfer per PPI_CLK cycle: * Data Receive with Internally Generated Frame Syncs * Data Receive with Externally Generated Frame Syncs * Data Transmit with Internally Generated Frame Syncs * Data Transmit with Externally Generated Frame Syncs These modes support ADC/DAC connections, as well as video communication with hardware signaling. Many of the modes support more than one level of frame synchronization. If desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data. although the changes are not realized until the Full-On mode is entered. DMA access is available to appropriately configured L1 memories. In the Active mode, it is possible to disable the PLL through the PLL Control register (PLL_CTL). If disabled, the PLL must be re-enabled before transitioning to the Full-On or Sleep modes. Table 4. Power Settings
PLL Core Bypassed Clock (CCLK) Full On Enabled No Enabled Active Enabled/ Yes Enabled Disabled Sleep Enabled Disabled Deep Sleep Disabled Disabled Hibernate Disabled Disabled Mode PLL System Core Clock Power (SCLK) Enabled On Enabled On Enabled On Disabled On Disabled Off
Hibernate Operating Mode--Maximum Static Power Savings
The Hibernate mode maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register. This disables both CCLK and SCLK. Furthermore, it sets the internal power supply voltage (VDDINT) to 0 V to provide the lowest static power dissipation. Any critical information stored internally (memory contents, register contents, etc.) must be written to a non-volatile storage device prior to removing power if the processor state is to be preserved. Since VDDEXT is still supplied in this mode, all of the external pins tri-state, unless otherwise specified. This allows other devices that may be connected to the processor to have power still applied without drawing unwanted current. The internal supply regulator can be woken up either by a RealTime Clock wakeup or by asserting the RESET pin.
DYNAMIC POWER MANAGEMENT
The ADSP-BF531/2/3 processor provides five operating modes, each with a different performance/power profile. In addition, Dynamic Power Management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. Control of clocking to each of the ADSP-BF531/2/3 processor peripherals also reduces power consumption. See Table 4 for a summary of the power settings for each mode.
Sleep Operating Mode--High Dynamic Power Savings
The Sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the processor. When in the Sleep mode, assertion of wakeup will cause the processor to sense the value of the BYPASS bit in the PLL Control register (PLL_CTL). If BYPASS is disabled, the processor will transition to the Full On mode. If BYPASS is enabled, the processor will transition to the Active mode. When in the Sleep mode, system DMA access to L1 memory is not supported.
Full-On Operating Mode--Maximum Performance
In the Full-On mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed.
Active Operating Mode--Moderate Power Savings
In the Active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor's core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. In this mode, the CLKIN to CCLK multiplier ratio can be changed,
Deep Sleep Operating Mode--Maximum Dynamic Power Savings
The Deep Sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals, such
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as the RTC, may still be running but will not be able to access internal resources or external memory. This powered-down mode can only be exited by assertion of the reset interrupt (RESET) or by an asynchronous interrupt generated by the RTC. When in Deep Sleep mode, an RTC asynchronous interrupt causes the processor to transition to the Active mode. Assertion of RESET while in Deep Sleep mode causes the processor to transition to the Full-On mode. * TNOM is the duration running at fCCLKNOM * TRED is the duration running at fCCLKRED The percent power savings is calculated as: % Power Savings = ( 1 - Power Savings Factor ) x 100%
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator that can generate processor core voltage levels 0.85V(-5% / +10%) to 1.2V(-5% / +10%) from an external 2.25 V to 3.6 V supply. Figure 7 shows the typical external components required to complete the power management system.* The regulator controls the internal logic voltage levels and is programmable with the Voltage Regulator Control Register (VR_CTL) in increments of 50 mV. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power (VDDEXT) supplied. While in hibernation, VDDEXT can still be applied, eliminating the need for external buffers. The voltage regulator can be activated from this power-down state either through an RTC wakeup or by asserting RESET, which will then initiate a boot sequence. The regulator can also be disabled and bypassed at the user's discretion.
Power Savings
As shown in Table 5, the ADSP-BF531/2/3 processor supports three different power domains. The use of multiple power domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating the internal logic of the ADSP-BF531/2/3 processor into its own power domain, separate from the RTC and other I/O, the processor can take advantage of Dynamic Power Management, without affecting the RTC or other I/O devices. There are no sequencing requirements for the various power domains. Table 5. Power Domains
Power Domain All internal logic, except RTC RTC internal logic and crystal I/O All other I/O VDD Range VDDINT VDDRTC VDDEXT
VDDEXT
The power dissipated by a processor is largely a function of the clock frequency of the processor and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic. The Dynamic Power Management feature of the ADSPBF531/2/3 processor allows both the processor's input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled. The savings in power dissipation can be modeled using the Power Savings Factor and % Power Savings calculations. The Power Savings Factor is calculated as: Power Savings Factor V DDINTRED 2 T RED f CCLKRED = -------------------- x ------------------------- x ------------ V DDINTNOM T NOM f CCLKNOM
100 F 10 H 0.1 F 100 F 1 F ZHCS1000
2.25V TO 3.6V INPUT VOLTAGE RANGE NDS8434
VDDINT
VROUT1-0
EXTERNAL COMPONENTS NOTE: VROUT1-0 SHOULD BE TIED TOGETHER EXTERNALLY AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO NDS8434.
Figure 7. Voltage Regulator Circuit
CLOCK SIGNALS
The ADSP-BF531/2/3 processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. If an external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor's CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected.
where the variables in the equations are: * fCCLKNOM is the nominal core clock frequency * fCCLKRED is the reduced core clock frequency * VDDINTNOM is the nominal internal supply voltage * VDDINTRED is the reduced internal supply voltage
*
See EE-228: Switching Regulator Design Considerations for ADSP-BF533 Blackfin Processors.
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Alternatively, because the ADSP-BF531/2/3 processor includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 8. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 6 illustrates typical system clock ratios. Table 6. Example System Clock Ratios
Signal Name SSEL3-0 0001 0011 1010 Divider Ratio Example Frequency Ratios VCO/SCLK (MHz) VCO SCLK 1:1 100 100 3:1 400 133 10:1 500 50
CLKIN
XTAL
CLKOUT
Figure 8. External Crystal Connections
The maximum frequency of the system clock is fSCLK. Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV). The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1-0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in Table 7. This programmable core clock capability is useful for fast core frequency modifications. Table 7. Core Clock Ratios
Signal Name CSEL1-0 00 01 10 11 Divider Ratio Example Frequency Ratios VCO/CCLK VCO CCLK 1:1 300 300 2:1 300 150 4:1 500 125 8:1 200 25
As shown in Figure 9 on Page 13, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a user programmable 1x to 63x multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 10x, but it can be modified by a software instruction sequence. On-the-fly frequency changes can be effected by simply writing to the PLL_DIV register.
"FI NE" ADJUSTMENT REQUI RES PLL SEQUENCING "COARSE" ADJUSTMENT ON-THE-FLY
/ 1, 2, 4, 8 CLKIN PLL 0. 5x - 64x
CCLK
VCO / 1:15 SCLK
BOOTING MODES
The ADSP-BF531/2/3 processor has two mechanisms (listed in Table 8) for automatically loading internal L1 instruction memory after a reset. A third mode is provided to execute from external memory, bypassing the boot sequence. Table 8. Booting Modes
BMODE1-0 00 01 10 11 Description Execute from 16-Bit External Memory (Bypass Boot ROM) Boot from 8-Bit or 16-Bit FLASH Reserved Boot from SPI Serial EEPROM (8-, 16-, or 24-Bit address range)
SCLK CCLK SCLK 133 MHZ
Figure 9. Frequency Modification Methods
All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3-0 bits of the PLL_DIV register. The values programmed
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The BMODE pins of the Reset Configuration Register, sampled during power-on resets and software-initiated resets, implement the following modes: * Execute from 16-bit external memory - Execution starts from address 0x2000 0000 with 16-bit packing. The boot ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup). * Boot from 8-bit or 16-bit external FLASH memory - The FLASH boot routine located in boot ROM memory space is set up using Asynchronous Memory Bank 0. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup). * Boot from SPI serial EEPROM (8, 16, or 24-bit addressable) - The SPI uses the PF2 output pin to select a single SPI EEPROM device, submits successive read commands at addresses 0x00, 0x0000, and 0x000000 until a valid 8, 16, or 24-bit addressable EEPROM is detected, and begins clocking data into the beginning of L1 instruction memory. For each of the boot modes, an 10-byte header is first read from an external memory device. The header specifies the number of bytes to be transferred and the memory destination address. Multiple memory blocks may be loaded by any boot sequence. Once all blocks are loaded, program execution commences from the start of L1 instruction SRAM. In addition, bit 4 of the Reset Configuration Register can be set by application code to bypass the normal boot sequence during a software reset. For this case, the processor jumps directly to the beginning of L1 instruction memory. * All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified programming model. * Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and supervisor stack pointers. * Code density enhancements, which include intermixing of 16- and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits.
DEVELOPMENT TOOLS
The ADSP-BF531/2/3 processor is supported with a complete set of CROSSCORE(R) software and hardware development tools, including Analog Devices emulators and VisualDSP++(R) development environment. The same emulator hardware that supports other Blackfin processors also fully emulates the ADSP-BF531/2/3 processor. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to processor assembly. The processor has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer's development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: * View mixed C/C++ and assembly code (interleaved source and object information). * Insert breakpoints.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor resources. The assembly language, which takes advantage of the processor's unique architecture, offers the following advantages: * Seamlessly integrated DSP/CPU features are optimized for both 8-bit and 16-bit operations. * A multi-issue load/store modified-Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle.

CROSSCORE is a registered trademark of Analog Devices, Inc. VisualDSP++ is a registered trademark of Analog Devices, Inc.
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* Set conditional breakpoints on registers, memory, and stacks. * Trace instruction execution. * Perform linear or statistical profiling of program execution. * Fill, dump, and graphically plot the contents of memory. * Perform source level debugging. * Create custom debugger windows. The VisualDSP++ IDDE lets programmers define and manage software development. Its dialog boxes and property pages let programmers configure and manage all of the Blackfin development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to: * Control how the development tools process inputs and generate outputs. * Maintain a one-to-one correspondence with the tool's command line switches. The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include Threads, Critical and Unscheduled regions, Semaphores, Events, and Device flags. The VDK also supports Priority-based, Preemptive, Cooperative, and Time-Sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the system state, when debugging an application that uses the VDK. VCSE is Analog Devices technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. Download components from the Web and drop them into the application. Publish component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language. Use the Expert Linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with the drag of the mouse, examine run time stack and heap usage. The Expert Linker is fully compatible with existing Linker Definition File (LDF), allowing the developer to move between the graphical and textual environments. Analog Devices emulators use the IEEE 1149.1 JTAG Test Access Port of the ADSP-BF531/2/3 processor to monitor and control the target board processor during emulation. The emuRev. 0 | Page 15 of 56 | March 2004
lator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor's JTAG interface--the emulator does not affect target system loading or timing. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the Blackfin processor family. Hardware tools include Blackfin processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.
DESIGNING AN EMULATOR COMPATIBLE PROCESSOR BOARD
The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG processor. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the processor's JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices web site (www.analog.com)-- use site search on "EE-68." This document is updated regularly to keep pace with improvements to emulator support.
ADSP-BF531/ADSP-BF532/ADSP-BF533
PIN DESCRIPTIONS
ADSP-BF531/2/3 processor pin definitions are listed in Table 9. All pins are three-stated during and immediately after reset, except the Memory Interface, Asynchronous Memory Control, and Synchronous Memory Control pins, which are driven high. If BR is active, then the memory pins are also three-stated. All unused I/O pins have their input buffers disabled with the exception of the pins that need pullups or pulldowns as noted in the table footnotes. Table 9. Pin Descriptions
Pin Name Memory Interface ADDR19-1 DATA15-0 ABE1-0/SDQM1-0 BR3 BG BGH Asynchronous Memory Control AMS3-0 ARDY AOE ARE AWE Synchronous Memory Control SRAS SCAS SWE SCKE CLKOUT SA10 SMS Timers TMR0 TMR1/PPI_FS1 TMR2/PPI_FS2 I/O Function O I/O O I O O O I O O O O O O O O O O Address Bus for Async/Sync Access Data Bus for Async/Sync Access Byte Enables/Data Masks for Async/Sync Access Bus Request Bus Grant Bus Grant Hang Bank Select Hardware Ready Control Output Enable Read Enable Write Enable Row Address Strobe Column Address Strobe Write Enable Clock Enable Clock Output A10 Pin Bank Select Driver Type1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 B4 A2 A2 C5 C5 C5
In order to maintain maximum functionality and reduce package size and pin count, some pins have dual, multiplexed functionality. In cases where pin functionality is reconfigurable, the default state is shown in plain text, while alternate functionality is shown in italics.
I/O Timer 0 I/O Timer 1/PPI Frame Sync1 I/O Timer 2/PPI Frame Sync2
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 9. Pin Descriptions (Continued)
Pin Name Parallel Peripheral Interface Port/GPIO PF0/SPISS PF1/SPISEL1/TMRCLK PF2/SPISEL2 PF3/SPISEL3/PPI_FS3 PF4/SPISEL4/PPI15 PF5/SPISEL5/PPI14 PF6/SPISEL6/PPI13 PF7/SPISEL7/PPI12 PF8/PPI11 PF9/PPI10 PF10/PPI9 PF11/PPI8 PF12/PPI7 PF13/PPI6 PF14/PPI5 PF15/PPI4 PPI3-0 PPI_CLK Serial Ports RSCLK0 RFS0 DR0PRI DR0SEC TSCLK0 TFS0 DT0PRI DT0SEC RSCLK1 RFS1 DR1PRI DR1SEC TSCLK1 TFS1 DT1PRI DT1SEC SPI Port MOSI MISO7 SCK I/O Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I I I/O I/O O O I/O I/O I I I/O I/O O O Programmable Flag 0/SPI Slave Select Input Programmable Flag 1/SPI Slave Select Enable 1/External Timer Reference Programmable Flag 2/SPI Slave Select Enable 2 Programmable Flag 3/SPI Slave Select Enable 3/PPI Frame Sync 3 Programmable Flag 4/SPI Slave Select Enable 4 / PPI 15 Programmable Flag 5/SPI Slave Select Enable 5 / PPI 14 Programmable Flag 6/SPI Slave Select Enable 6 / PPI 13 Programmable Flag 7/SPI Slave Select Enable 7 / PPI 12 Programmable Flag 8/PPI 11 Programmable Flag 9/PPI 10 Programmable Flag 10/PPI 9 Programmable Flag 11/PPI 8 Programmable Flag 12/PPI 7 Programmable Flag 13/PPI 6 Programmable Flag 14/PPI 5 Programmable Flag 15/PPI 4 PPI3-0 PPI Clock SPORT0 Receive Serial Clock SPORT0 Receive Frame Sync SPORT0 Receive Data Primary SPORT0 Receive Data Secondary SPORT0 Transmit Serial Clock SPORT0 Transmit Frame Sync SPORT0 Transmit Data Primary SPORT0 Transmit Data Secondary SPORT1 Receive Serial Clock SPORT1 Receive Frame Sync SPORT1 Receive Data Primary SPORT1 Receive Data Secondary SPORT1 Transmit Serial Clock SPORT1 Transmit Frame Sync SPORT1 Transmit Data Primary SPORT1 Transmit Data Secondary Driver Type1 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 D6 C5
D6 C5 C5 C5 D6 C5
D6 C5 C5 C5 C5 C5 D6
I/O Master Out Slave In I/O Master In Slave Out I/O SPI Clock
Rev. 0 |
Page 17 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 9. Pin Descriptions (Continued)
Pin Name UART Port RX TX Real Time Clock RTXI8 RTXO JTAG Port TCK TDO TDI TMS TRST9 EMU Clock CLKIN XTAL Mode Controls RESET NMI8 BMODE1-0 Voltage Regulator VROUT1-0 Supplies VDDEXT VDDINT VDDRTC GND
1 2
I/O Function I O I O I O I I I O I O I I I O P P P G UART Receive UART Transmit RTC Crystal Input RTC Crystal Output JTAG Clock JTAG Serial Data Out JTAG Serial Data In JTAG Mode Select JTAG Reset Emulation Output Clock/Crystal Input Crystal Output Reset Non-maskable Interrupt Boot Mode Strap External FET Drive I/O Power Supply Core Power Supply Real Time Clock Power Supply External Ground
Driver Type1
C5
C5
C5
Refer to Figure 26 on Page 39 to Figure 30 on Page 40. See Figure 25 and Figure 26 on Page 39 3 This pin should be pulled HIGH when not used. 4 See Figure 27 and Figure 28 on Page 39 5 See Figure 29 and Figure 30 on Page 40 6 See Figure 31 and Figure 32 on Page 40 7 This pin should always be pulled HIGH through a 4.7K Ohm resistor if booting via the SPI port. 8 This pin should always be pulled LOW when not used. 9 This pin should be pulled LOW if the JTAG port will not be used.
Rev. 0 |
Page 18 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
SPECIFICATIONS
Component specifications are subject to change without notice.
RECOMMENDED OPERATING CONDITIONS
Parameter VDDINT VDDEXT VDDRTC VIH VIHCLKIN VIL
1
Internal Supply Voltage External Supply Voltage Real-time Clock Power Supply Voltage High Level Input Voltage1, 2 @ VDDEXT =maximum High Level Input Voltage3 @ VDDEXT =maximum Low Level Input Voltage2, 4 @ VDDEXT =minimum
Minimum 0.8 2.25 2.25 2.0 2.2 -0.3
Nominal 1.2 2.5 or 3.3
Maximum 1.32 3.6 3.6 3.6 3.6 0.6
Unit V V V V V V
The ADSP-BF531/2/3 processor is 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because VOH (maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bidirectional pins (DATA15-0, TMR2-0, PF15-0, PPI3-0, RSCLK1-0, TSCLK1-0, RFS1-0, TFS1-0, MOSI, MISO, SCK) and input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE1-0). 2 Parameter value applies to all input and bidirectional pins except CLKIN. 3 Parameter value applies to CLKIN pin only. 4 Parameter value applies to all input and bidirectional pins.
ELECTRICAL CHARACTERISTICS
Parameter VOH VOL IIH IIHP IIL IOZH IOZL CIN
1 2
High Level Output Voltage Low Level Output Voltage2 High Level Input Current2 High Level Input Current JTAG3 Low Level Input Current4 Three-State Leakage Current4 Three-State Leakage Current5 Input Capacitance5, 6
1
Test Conditions @ VDDEXT =3.0V, IOH = -0.5 mA @ VDDEXT =3.0V, IOL = 2.0 mA @ VDDEXT =maximum, VIN = VDD maximum @ VDDEXT =maximum, VIN = VDD maximum @ VDDEXT =maximum, VIN = 0 V @ VDDEXT = maximum, VIN = VDD maximum @ VDDEXT = maximum, VIN = 0 V fIN = 1 MHz, TAMBIENT = 25C, VIN = 2.5 V
Minimum 2.4
Maximum 0.4 10.0 20.0 10.0 10.0 10.0 8.0
Unit V V A A A A A pF
Applies to output and bidirectional pins. Applies to input pins except JTAG inputs. 3 Applies to JTAG input pins (TCK, TDI, TMS, TRST). 4 Applies to three-statable pins. 5 Applies to all signal pins. 6 Guaranteed, but not tested.
Rev. 0 |
Page 19 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in the table may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at 3.3 V) or 30 pF (at 2.5 V) for ADDR19-1, DATA15-0, ABE1-0/SDQM1-0, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS.
Parameter Internal (Core) Supply Voltage (VDDINT) External (I/O) Supply Voltage (VDDEXT) Input Voltage Output Voltage Swing Load Capacitance ADSP-BF533 Core Clock (CCLK) ADSP-BF532/BF531 Core Clock (CCLK) Peripheral Clock (SCLK) Storage Temperature Range Junction Temperature Under Bias Rating -0.3 V to +1.4 V -0.3 V to +3.8 V -0.5 V to 3.6 V -0.5 V to VDDEXT +0.5 V 200 pF 600 MHz 400 MHz 133 MHz -65C to +150C 125C
ESD SENSITIVITY
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-BF531/2/3 processor features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 |
Page 20 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
TIMING SPECIFICATIONS
Table 10 through Table 14 describe the timing requirements for the ADSP-BF531/2/3 processor clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock as described in Absolute Maximum Ratings on Page 20, and the Voltage Controlled Oscillator (VCO) operating frequencies described in Table 13. Table 13 describes Phase-Locked Loop operating conditions.
Table 10. Core and System Clock Requirements--ADSP-BF533SKBC600
Parameter tCCLK Core Cycle Period (VDDINT =1.2 V-5%) Core Cycle Period (VDDINT =1.1 V-5%) tCCLK tCCLK Core Cycle Period (VDDINT =1.0 V-5%) tCCLK Core Cycle Period (VDDINT =0.9 V-5%) tCCLK Core Cycle Period (VDDINT =0.8 V) tSCLK System Clock Period Min 1.67 2.10 2.35 2.66 4.00 Maximum of 7.5 or tCCLK Max Unit ns ns ns ns ns ns
Table 11. Core and System Clock Requirements--ADSP-BF533SBBC500 and ADSP-BF533SBBZ500
Parameter tCCLK Core Cycle Period (VDDINT =1.2 V-5%) tCCLK Core Cycle Period (VDDINT =1.1 V-5%) Core Cycle Period (VDDINT =1.0 V-5%) tCCLK tCCLK Core Cycle Period (VDDINT =0.9 V-5%) tCCLK Core Cycle Period (VDDINT =0.8 V) tSCLK System Clock Period Min 2.0 2.25 2.50 3.00 4.00 Maximum of 7.5 or tCCLK Max Unit ns ns ns ns ns ns
Table 12. Core and System Clock Requirements--ADSP-BF532/531 All Package Types
Parameter tCCLK Core Cycle Period (VDDINT =1.2 V-5%) tCCLK Core Cycle Period (VDDINT =1.1 V-5%) tCCLK Core Cycle Period (VDDINT =1.0 V-5%) tCCLK Core Cycle Period (VDDINT =0.9 V-5%) tCCLK Core Cycle Period (VDDINT =0.8 V) tSCLK System Clock Period Min 2.5 2.75 3.00 3.25 4.0 Maximum of 7.5 or tCCLK Max Unit ns ns ns ns ns ns
Table 13. Phase-Locked Loop Operating Conditions
Parameter fVCO Voltage Controlled Oscillator (VCO) Frequency Min 50 Max Max CCLK Unit MHz
Table 14. Maximum SCLK Conditions
Parameter MBGA fSCLK fSCLK LQFP fSCLK fSCLK
1
Condition
VDDEXT = 3.3 V
VDDEXT = 2.5 V
Unit
VDDINT >= 1.14 V VDDINT < 1.14 V VDDINT >= 1.14 V VDDINT < 1.14 V
133 100 133 83
133 100 1331 831
MHz MHz MHz MHz
Set bit 7 (output delay) of PLL_CTL register.
Rev. 0 |
Page 21 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Clock and Reset Timing
Table 15 and Figure 10 describe clock and reset operations. Per Absolute Maximum Ratings on Page 20, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 600/133 MHz. Table 15. Clock and Reset Timing
Parameter Timing Requirements tCKIN CLKIN Period tCKINL CLKIN Low Pulse1 CLKIN High Pulse1 tCKINH tWRST RESET Asserted Pulse Width Low2
1 2
Min 25.0 10.0 10.0 11 tCKIN
Max 100.0
Unit ns ns ns ns
Applies to bypass mode and non-bypass mode. Applies after power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted, assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
tCKIN
CLKIN
tCKINL
RESET
tCKINH tWRST
Figure 10. Clock and Reset Timing
Rev. 0 |
Page 22 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Read Cycle Timing
Table 16. Asynchronous Memory Read Cycle Timing
Parameter Timing Requirements tSDAT DATA15-0 Setup Before CLKOUT tHDAT DATA15-0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDO Output Delay After CLKOUT1 Output Hold After CLKOUT 1 tHO
1
Min 2.1 0.8 4.0 0.0
Max
Unit ns ns ns ns
6.0 0.8
ns ns
Output pins include AMS3-0, ABE1-0, ADDR19-1, AOE, ARE.
SETUP 2 CYCLES
PROGRAMMED READ ACCESS 4 CYCLES
ACCESS EXTENDED 3 CYCLES
HOLD 1 CYCLE
CLKOUT
t DO
AMSx
t HO
ABE1-0 ADDR19-1
BE, ADDRESS
AOE
t DO
ARE
tHO
t SARDY
ARDY
tHARDY
t HARDY
t SARDY
t SDAT t HDAT
DATA15-0
READ
Figure 11. Asynchronous Memory Read Cycle Timing
Rev. 0 |
Page 23 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Write Cycle Timing
Table 17. Asynchronous Memory Write Cycle Timing
Parameter Timing Requirements tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDDAT DATA15-0 Disable After CLKOUT tENDAT DATA15-0 Enable After CLKOUT tDO Output Delay After CLKOUT1 Output Hold After CLKOUT 1 tHO
1
Min 4.0 0.0
Max
Unit ns ns
6.0 1.0 6.0 0.8
ns ns ns ns
Output pins include AMS3-0, ABE1-0, ADDR19-1, DATA15-0, AOE, AWE.
SETUP 2 CYCLES
PROGRAMMED WRITE ACCESS 2 CYCLES
ACCESS EXTENDED 1 CYCLE
HOLD 1 CYCLE
CLKOUT
t DO
AMSx
t HO
ABE1-0 ADDR19-1
BE, ADDRESS
tDO
AWE
tHO
t SARDY
ARDY
t HARDY
t END AT
DATA15-0 WRITE DATA
tSARDY
t DD AT
Figure 12. Asynchronous Memory Write Cycle Timing
Rev. 0 |
Page 24 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
SDRAM Interface Timing
Table 18. SDRAM Interface Timing1
Parameter Timing Requirements tSSDAT DATA Setup Before CLKOUT tHSDAT DATA Hold After CLKOUT Switching Characteristics tSCLK CLKOUT Period tSCLKH CLKOUT Width High tSCLKL CLKOUT Width Low Command, ADDR, Data Delay After CLKOUT2 tDCAD tHCAD Command, ADDR, Data Hold After CLKOUT1 tDSDAT Data Disable After CLKOUT tENSDAT Data Enable After CLKOUT
1 2
Min 2.1 0.8 7.5 2.5 2.5
Max
Unit ns ns ns ns ns ns ns ns ns
6.0 0.8 6.0 1.0
For VDDINT = 1.2 V. Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
tSCLK
CLKOUT
tSCLKH
t SSDAT tHSDAT
DATA (IN)
t SCLKL
t DCAD tENSDAT
DATA(OUT)
tD SDA T tHCAD
tDCAD
CMND ADDR (OUT)
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 13. SDRAM Interface Timing
Rev. 0 |
Page 25 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
External Port Bus Request and Grant Cycle Timing
Table 19 and Figure 14 describe external port bus request and bus grant operations. Table 19. External Port Bus Request and Grant Cycle Timing
Parameter, 1, 2 Timing Requirements tBS BR Asserted to CLKOUT High Setup tBH CLKOUT High to BR Deasserted Hold Time Switching Characteristics tSD CLKOUT Low to xMS, Address, and RD/WR disable CLKOUT Low to xMS, Address, and RD/WR enable tSE tDBG CLKOUT High to BG High Setup tEBG CLKOUT High to BG Deasserted Hold Time tDBH CLKOUT High to BGH High Setup tEBH CLKOUT High to BGH Deasserted Hold Time
1 2
Min 4.6 0.0
Max
Unit ns ns
4.5 4.5 3.6 3.6 3.6 3.6
ns ns ns ns ns ns
These are preliminary timing parameters that are based on worst-case operating conditions. The pad loads for these timing parameters are 20 pF.
CLKOUT
tBS
BR
tBH
tSD
AMSx
tSE
tSD
tSE
ADDR19-1 ABE1-0
tSD
tSE
AWE ARE
tDBG
BG
tEBG
tDBH
BGH
TEBH
Figure 14. External Port Bus Request and Grant Cycle Timing
Rev. 0 |
Page 26 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Parallel Peripheral Interface Timing
Table 20 and Figure 15 on Page 27 describe Parallel Peripheral Interface operations. Table 20. Parallel Peripheral Interface Timing
Parameter Timing Requirements tPCLKW PPI_CLK Width tPCLK PPI_CLK Period1 tSFSPE External Frame Sync Setup Before PPI_CLK tHFSPE External Frame Sync Hold After PPI_CLK Receive Data Setup Before PPI_CLK tSDRPE tHDRPE Receive Data Hold After PPI_CLK Switching Characteristics - GP Output and Frame Capture Modes tDFSPE Internal Frame Sync Delay After PPI_CLK tHOFSPE Internal Frame Sync Hold After PPI_CLK tDDTPE Transmit Data Delay After PPI_CLK Transmit Data Hold After PPI_CLK tHDTPE
1
Min 6.0 15.0 3.0 3.0 2.0 4.0
Max
Unit ns ns ns ns ns ns
10.0 0.0 10.0 0.0
ns ns ns ns
PPI_CLK frequency cannot exceed fSCLK/2
DRIVE EDGE
SAMPLE EDGE
tPCLKW
PPI_CLK
tDFSPE tHOFSPE
PPI_FS1 PPI_FS2
tSFSPE
tHFSPE
tDDTPE tHDTPE
PPIx
tSDRPE
tHDRPE
Figure 15. GP Output Mode and Frame Capture Timing
Rev. 0 |
Page 27 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Ports
Table 21 through Table 26 on Page 29 and Figure 16 on Page 30 through Figure 18 on Page 32 describe Serial Port operations. Table 21. Serial Ports--External Clock
Parameter Timing Requirements tSFSE TFS/RFS Setup Before TSCLK/RSCLK1 tHFSE TFS/RFS Hold After TSCLK/RSCLK1 tSDRE Receive Data Setup Before RSCLK1 tHDRE Receive Data Hold After RSCLK1 TSCLK/RSCLK Width tSCLKEW tSCLKE TSCLK/RSCLK Period
1
Min 3.0 3.0 3.0 3.0 4.5 15.0
Max
Unit ns ns ns ns ns ns
Referenced to sample edge.
Table 22. Serial Ports--Internal Clock
Parameter Timing Requirements tSFSI TFS/RFS Setup Before TSCLK/RSCLK1 tHFSI TFS/RFS Hold After TSCLK/RSCLK1 tSDRI Receive Data Setup Before RSCLK1 tHDRI Receive Data Hold After RSCLK1 tSCLKEW TSCLK/RSCLK Width tSCLKE TSCLK/RSCLK Period
1
Min 8.0 -2.0 6.0 0.0 4.5 15.0
Max
Unit ns ns ns ns ns ns
Referenced to sample edge.
Table 23. Serial Ports--External Clock
Parameter Switching Characteristics tDFSE TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)1 tHOFSE TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1 tDDTE Transmit Data Delay After TSCLK1 Transmit Data Hold After TSCLK1 tHDTE
1
Min
Max 10.0
Unit ns ns ns ns
0.0 10.0 0.0
Referenced to drive edge.
Table 24. Serial Ports--Internal Clock
Parameter Switching Characteristics tDFSI TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)1 TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1 tHOFSI tDDTI Transmit Data Delay After TSCLK1 tHDTI Transmit Data Hold After TSCLK1 tSCLKIW TSCLK/RSCLK Width
1
Min
Max 3.0
Unit ns ns ns ns ns
-1.0 3.0 -2.0 4.5
Referenced to drive edge.
Rev. 0 |
Page 28 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 25. Serial Ports--Enable and Three-State
Parameter Switching Characteristics tDTENE Data Enable Delay from External TSCLK1 Data Disable Delay from External TSCLK1 tDDTTE tDTENI Data Enable Delay from Internal TSCLK1 tDDTTI Data Disable Delay from Internal TSCLK1
1
Min 0
Max
Unit ns ns ns ns
10.0 -2.0 3.0
Referenced to drive edge.
Table 26. External Late Frame Sync
Parameter Switching Characteristics Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01, 2 tDDTLFSE tDTENLFSE Data Enable from late FS or MCE = 1, MFD = 01,2
1
Min
Max 10.0
Unit ns ns
0
MCE = 1, TFS enable and TFS valid follow tDDTENFS and tDDTLFSE. 2 If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTLSCK and tDTENLSCK apply; otherwise tDDTLFSE and tDTENLFS apply.
Rev. 0 |
Page 29 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
DATA RECEIVE- INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA RECEIVE- EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
RSCLK RSCLK
tSCLKEW
tDFSE tHOFSE
RFS
tDFSE tSFSI tHFSI
RFS
tHOFSE
tSFSE
tHFSE
tSDRI
DR
tHDRI
DR
tSDRE
tHDRE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT- INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA TRANSMIT- EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
TSCLK TSCLK
tSCLKEW
tDFSI tHOFSI
TFS
tDFSE tSFSI tHFSI
TFS
tHOFSE
tSFSE
tHFSE
tDDTI tHDTI
DT DT
tDDTE tHDTE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE TSCLK (EXT) TFS ("LATE", EXT.) TSCLK / RSCLK DRIVE EDGE
tDTENE
DT DRIVE EDGE TSCLK (INT) TFS ("LATE", INT.) TSCLK / RSCLK DRIVE EDGE
tDDTTE
tDTENI
DT
tDDTTI
Figure 16. Serial Ports
Rev. 0 |
Page 30 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE RSCLK
SAMPLE
DRIVE
tSFSE/I
RFS
tHOFSE/I
tDDTE/I tDDTENFS
DT
tHDTE/I
2ND BIT
1ST BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE TSCLK
SAMPLE
DRIVE
tSFSE/I
TFS
tHOFSE/I
tDDTE/I tDDTENFS
DT 1ST BIT
tHDTE/I
2ND BIT
tDDTLFSE
Figure 17. External Late Frame Sync (Frame Sync Setup < tSCLKE/2)
Rev. 0 |
Page 31 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
EXTERNAL RFS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE
RSCLK
tSFSE/I
tHOFSE/I
RFS
tDDTE/I tDTENLSCK
DT 1ST BIT
tHDTE/I
2ND BIT
tDDTLSCK
LATE EXTERNAL TFS DRIVE SAMPLE DRIVE
TSCLK
tSFSE/I
tHOFSE/I
TFS
tDDTE/I tDTENLSCK
DT 1ST BIT
tHDTE/I
2ND BIT
tDDTLSCK
Figure 18. External Late Frame Sync (Frame Sync Setup > tSCLKE/2)
Rev. 0 |
Page 32 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port --Master Timing
Table 27 and Figure 19 describe SPI port master operations. Table 27. Serial Peripheral Interface (SPI) Port--Master Timing
Parameter Timing Requirements tSSPIDM Data Input Valid to SCK Edge (Data Input Setup) tHSPIDM SCK Sampling Edge to Data Input Invalid Switching Characteristics tSDSCIM SPISELx Low to First SCK edge (x=0 or 1) tSPICHM Serial Clock High period tSPICLM Serial Clock Low period tSPICLK Serial Clock Period tHDSM Last SCK Edge to SPISELx High (x=0 or 1) Sequential Transfer Delay tSPITDM tDDSPIDM SCK Edge to Data Out Valid (Data Out Delay) tHDSPIDM SCK Edge to Data Out Invalid (Data Out Hold) Min 7.5 -1.5 2tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 4tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 0 -1.0 Max Unit ns ns ns ns ns ns ns ns ns ns
6 4.0
SPISELx (OUTPUT)
tSDSCIM
SCK (CPOL = 0) (OUTPUT)
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tSPICLM
SCK (CPOL = 1) (OUTPUT)
tSPICHM
tDDSPIDM
MOSI (OUTPUT) CPHA=1 MISO (INPUT) MSB
tHDSPIDM
LSB
tSSPIDM
MSB VALID
tHSPIDM
tSSPIDM
LSB VALID
tHSPIDM
tDDSPIDM
MOSI (OUTPUT) CPHA=0 MISO (INPUT) MSB
tHDSPIDM
LSB
tSSPIDM
MSB VALID
tHSPIDM
LSB VALID
Figure 19. Serial Peripheral Interface (SPI) Port--Master Timing
Rev. 0 |
Page 33 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port --Slave Timing
Table 28 and Figure 20 describe SPI port slave operations. Table 28. Serial Peripheral Interface (SPI) Port--Slave Timing
Parameter Timing Requirements tSPICHS Serial Clock High Period tSPICLS Serial Clock low Period Serial Clock Period tSPICLK tHDS Last SCK Edge to SPISS Not Asserted tSPITDS Sequential Transfer Delay tSDSCI SPISS Assertion to First SCK Edge tSSPID Data Input Valid to SCK Edge (Data Input Setup) tHSPID SCK Sampling Edge to Data Input Invalid Switching Characteristics tDSOE SPISS Assertion to Data Out Active tDSDHI SPISS Deassertion to Data High impedance tDDSPID SCK Edge to Data Out Valid (Data Out Delay) tHDSPID SCK Edge to Data Out Invalid (Data Out Hold) Min 2tSCLK -1.5 2tSCLK -1.5 4tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 1.6 1.6 0 0 0 0 8 8 10 10 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns
SPISS (INPUT)
tSPICHS
SCK (CPOL = 0) (INPUT)
tSPICLS
tSPICLK
tHDS
tSPITDS
tSDSCI
SCK (CPOL = 1) (INPUT)
tSPICLS
tSPICHS
tDSOE
tDDSPID tHDSPID tDDSPID tDSDHI
LSB
MISO (OUTPUT) CPHA=1 MOSI (INPUT)
MSB
tSSPID
MSB VALID
tHSPID
tSSPID
tHSPID
LSB VALID
tDSOE
MISO (OUTPUT) CPHA=0 MOSI (INPUT)
tDDSPID
MSB LSB
tDSDHI
tHSPID tSSPID
MSB VALID LSB VALID
Figure 20. Serial Peripheral Interface (SPI) Port--Slave Timing
Rev. 0 |
Page 34 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Universal Asynchronous Receiver-Transmitter (UART) Port--Receive and Transmit Timing
Figure 21 describes UART port receive and transmit operations. The maximum baud rate is SCLK/16. As shown in Figure 21 there is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART.
CLKOUT (SAMPLE CLOCK)
RXD
DATA(5-8) STOP
RECEIVE INTERNAL UART RECEIVE INTERRUPT
UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ
START TXD DATA(5-8) STOP (1-2)
TRANSMIT INTERNAL UART TRANSMIT INTERRUPT UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT
Figure 21. UART Port--Receive and Transmit Timing
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Programmable Flags Cycle Timing
Table 29 and Figure 22 describe programmable flag operations. Table 29. Programmable Flags Cycle Timing
Parameter Timing Requirements tWFI Flag Input Pulse Width Switching Characteristics Flag Output Delay from CLKOUT Low tDFO Min tSCLK + 1 6 Max Unit ns ns
CLKOUT
tDFO
PF (OUTPUT) FLAG OUTPUT
tWFI
PF (INPUT) FLAG INPUT
Figure 22. Programmable Flags Cycle Timing
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Timer Cycle Timing
Table 30 and Figure 23 describe timer expired operations. The input signal is asynchronous in "width capture mode" and "external clock mode" and has an absolute maximum input frequency of fSCLK/2 MHz. Table 30. Timer Cycle Timing
Parameter Timing Characteristics tWL Timer Pulse Width Input Low1 (Measured in SCLK Cycles) tWH Timer Pulse Width Input High1 (Measured in SCLK Cycles) Switching Characteristics tHTO Timer Pulse Width Output2 (Measured in SCLK Cycles)
1 2
Min 1 1 1
Max
Unit SCLK SCLK
(232-1)
SCLK
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode. The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232-1) cycles.
CLKOUT
tHTO
TMRx (PWM OUTPUT MODE)
TMRx (WIDTH CAPTURE AND EXTERNAL CLOCK MODES)
tWL
tWH
Figure 23. Timer PWM_OUT Cycle Timing
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ADSP-BF531/ADSP-BF532/ADSP-BF533
JTAG Test And Emulation Port Timing
Table 31 and Figure 24 describe JTAG port operations. Table 31. JTAG Port Timing
Parameter Timing Requirements tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High TDI, TMS Hold After TCK High tHTAP tSSYS System Inputs Setup Before TCK High1 tHSYS System Inputs Hold After TCK High1 tTRSTW TRST Pulse Width2 (Measured in TCK cycles) Switching Characteristics tDTDO TDO Delay from TCK Low System Outputs Delay After TCK Low3 tDSYS
1
Min 20 4 4 4 5 4
Max
Unit ns ns ns ns ns TCK
0
10 12
ns ns
System Inputs=DATA15-0, ARDY, TMR2-0, PF15-0, PPI_CLK, RSCLK0-1, RFS0-1, DR0PRI, DR0SEC, TSCLK0-1, TFS0-1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX, RESET, NMI, BMODE1-0, BR, PP3-0. 2 50 MHz maximum 3 System Outputs=DATA15-0, ADDR19-1, ABE1-0, AOE, ARE, AWE, AMS3-0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2-0, PF15-0, RSCLK0-1, RFS0-1, TSCLK0-1, TFS0-1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3-0.
tTCK
TCK
tSTAP
TMS TDI
tHTAP
tDTDO
TDO
tSSYS
SYSTEM INPUTS
tHSYS
tDSYS
SYSTEM OUTPUTS
Figure 24. JTAG Port Timing
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ADSP-BF531/ADSP-BF532/ADSP-BF533
OUTPUT DRIVE CURRENTS
Figure 25 through Figure 32 show typical current-voltage characteristics for the output drivers of the ADSP-BF531/2/3 processor. The curves represent the current drive capability of the output drivers as a function of output voltage.
SOURCE CURRENT (mA) 150 VDDEXT = 2.25V @ 95C VDDEXT = 2.50V @ 25C VDDEXT = 2.75V @ -40C
100
50
150 = 2.25V @ 95C DDEXT VDDEXT = 2.50V @ 25C V = 2.75V @ -40C DDEXT V
0
V OH
100 SOURCE CURRENT (mA)
-50
50
-100
VOL
0
VOH
-150
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V) -50
-100
V
Figure 27. Drive Current B (Low VDDEXT)
OL
-150
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
150
V
Figure 25. Drive Current A (Low VDDEXT)
100 SOURCE CURRENT (mA)
= 2.95V @ 95C DDEXT = 3.30V @ 25C DDEXT V = 3.65V @ -40C DDEXT V
50
150 VDDEXT = 2.95V @ 95C V = 3.30V @ 25C DDEXT VDDEXT = 3.65V @ -40C
0 VOH -50
100 SOURCE CURRENT (mA)
50
-100 V OL
0 V -50 OH
-150 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) 2.5 3.0 3.5
-100
VOL
Figure 28. Drive Current B (High VDDEXT)
-150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
SOURCE VOLTAGE (V)
Figure 26. Drive Current A (High VDDEXT)
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ADSP-BF531/ADSP-BF532/ADSP-BF533
100 80 40 = 2.25V @ 95C DDEXT VDDEXT = 2.50V @ 25C V = 2.75V @ -40C DDEXT V 60 SOURCE CURRENT (mA) 40 20 0 -20 -40 -60 -40 -80 -60 VOL 0 0.5 1.0 1.5 2.0 2.5 3.0 SOURCE VOLTAGE (V) -100 0 0.5 1.0 1.5 2.0 2.5 3.0 VOL VOH VDDEXT = 2.25V @ 95C VDDEXT = 2.50V @ 25C VDDEXT = 2.75V @ -40C
60
20 SOURCE CURRENT (mA)
0
-20
V
OH
SOURCE VOLTAGE (V)
Figure 29. Drive Current C (Low VDDEXT)
Figure 31. Drive Current D (Low VDDEXT)
80 60 SOURCE CURRENT (mA) 40 20 0 -20 -40 -60 -80
V V V
DDEXT
DDEXT DDEXT
= 2.95V @ 95C = 3.30V @ 25C = 3.65V @ -40C SOURCE CURRENT (mA)
150
100
VDDEXT = 2.95V @ 95C VDDEXT = 3.30V @ 25C V = 3.65V @ -40C DDEXT
50
0
VOH
V
OH
-50 VOL
VOL
-100
-150 -100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) 2.5 3.0 3.5
SOURCE VOLTAGE (V)
Figure 30. Drive Current C (High VDDEXT)
Figure 32. Drive Current D (High VDDEXT)
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ADSP-BF531/ADSP-BF532/ADSP-BF533
POWER DISSIPATION
Total power dissipation has two components: one due to internal circuitry (PINT) and one due to the switching of external output drivers (PEXT). Table 32 shows the power dissipation for internal circuitry (VDDINT). Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Table 32. Internal Power Dissipation1
Test Conditions2 fCCLK = fCCLK = 50 MHz 400 MHz VDDINT = VDDINT = 0.8 V 1.2 V 26 160 16 37 14 31 50 30
Parameter
IDDTYP3 IDDSLEEP4 IDDDEEPSLEEP4 IDDHIBERNATE5 IDDRTC6
1 2
fCCLK = 500 MHz VDDINT = 1.2 V 190 37 31
fCCLK = 600 MHz VDDINT = 1.2 V 220 37 31
Unit
mA mA mA A A
See EE-229: Estimating Power for ADSP-BF533 Blackfin Processors. IDD data is specified for typical process parameters. All data at 25C. 3 Processor executing 75% dual Mac, 25% ADD with moderate data bus activity. 4 See the ADSP-BF53x Blackfin Processor Hardware Reference Manual for definitions of Sleep and Deep Sleep operating modes. 5 Measured at VDDEXT = 3.65V with voltage regulator off (VDDINT = 0V). 6 Measured at VDDRTC = 3.3V at 25C.
The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on: * Number of output pins (O) that switch during each cycle * Maximum frequency (f) at which they can switch * Their load capacitance (C) * Their voltage swing (VDDEXT) The external component is calculated using: P EXT = O x C x V
2 DD
xf
The frequency f includes driving the load high and then back low. For example: DATA15-0 pins can drive high and low at a maximum rate of 1/(2 tSCLK) while in SDRAM burst mode. A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: P TOTAL = P EXT + ( I DD x V DDINT ) Note that the conditions causing a worst-case PEXT differ from those causing a worst-case PINT . Maximum PINT cannot occur while 100% of the output pins are switching from all ones (1s) to all zeros (0s). Note, as well, that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously.
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ADSP-BF531/ADSP-BF532/ADSP-BF533
TEST CONDITIONS
All timing parameters appearing in this data sheet were measured under the conditions described in this section.
REFERENCE SIGNAL
Output Enable Time
Output pins are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. The output enable time tENA is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown in the Output Enable/Disable diagram (Figure 33). The time tENA_MEASURED is the interval from when the reference signal switches to when the output voltage reaches 2.0 V (output high) or 1.0 V (output low). Time tTRIP is the interval from when the output starts driving to when the output reaches the 1.0 V or 2.0 V trip voltage. Time tENA is calculated as shown in the equation: t ENA = t ENA_MEASURED - t TRIP If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
tDIS_MEASURED tDIS
VOH (MEASURED) VOL (MEASURED)
tENA-MEASURED tENA
VOH (MEASURED)
V
VOH 2.0V (MEASURED) 1.0V VOL (MEASURED)
VOL (MEASURED) + V
tDECAY
tTRIP
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1.5V.
Figure 33. Output Enable/Disable
TO OUTPUT PIN 30pF
50 OHMS 1.5V
Output Disable Time
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by V is dependent on the capacitive load, CL and the load current, IL. This decay time can be approximated by the equation: t DECAY = ( C L V ) I L The output disable time tDIS is the difference between tDIS_MEASURED and tDECAY as shown in Figure 33. The time tDIS_MEASURED is the interval from when the reference signal switches to when the output voltage decays V from the measured output high or output low voltage. The time tDECAY is calculated with test loads CL and IL, and with V equal to 0.5 V.
Figure 34. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
INPUT OR OUTPUT
1.5V
1.5V
Figure 35. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
delay and hold specifications given should be derated by a factor derived from these figures. The graphs in these figures may not be linear outside the ranges shown.
Example System Hold Time Calculation
To determine the data output hold time in a particular system, first calculate tDECAY using the equation given above. Choose V to be the difference between the ADSP-BF531/2/3 processor's output voltage and the input threshold for the device requiring the hold time. A typical V will be 0.4 V. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the minimum disable time (for example, tDSDAT for an SDRAM write cycle).
Capacitive Loading
Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 34). Figure 36 through Figure 43 on Page 44 show how output rise time varies with capacitance. The
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ADSP-BF531/ADSP-BF532/ADSP-BF533
12 RISE AND FALL TIME NS (10%-90%) 14 RISE AND FALL TIME NS (10%-90%)
CLKOUT (CLKOUT DRIVER), EVDDMIN = 2.25V, TEMPERATURE = 85C
ABE_B[0] (133 MHZ DRIVER), EVDDMIN = 2.25V, TEMPERATURE = 85C
10
12
RISE TIME
8 FALL TIME
RISE TIME
10 8 FALL TIME
6
6 4
4
2
2 0 0
0
50
0
50
100 150 LOAD CAPACITANCE (PF)
200
250
100 150 LOAD CAPACITANCE (PF)
200
250
Figure 38. Typical Output Delay or Hold for Driver B at EVDDMIN Figure 36. Typical Output Delay or Hold for Driver A at EVDDMIN
10
CLKOUT (CLKOUT DRIVER), EVDDMAX = 3.65V, TEMPERATURE = 85C
ABE0 (133 MHZ DRIVER), EVDDMAX = 3.65V, TEMPERATURE = 85C
12 RISE AND FALL TIME NS (10%-90%) RISE AND FALL TIME NS (10%-90%) 9 8
10
RISE TIME
7 6 FALL TIME 5 4 3 2 1 0
RISE TIME
8 FALL TIME 6
4
2
0
50
0
0
50
100 150 LOAD CAPACITANCE (PF)
200
250
100 150 LOAD CAPACITANCE (PF)
200
250
Figure 39. Typical Output Delay or Hold for Driver B at EVDDMAX Figure 37. Typical Output Delay or Hold for Driver A at EVDDMAX
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ADSP-BF531/ADSP-BF532/ADSP-BF533
30 RISE AND FALL TIME NS (10%-90%)
TMR0 (33 MHZ DRIVER), EVDDMIN = 2.25V, TEMPERATURE = 85C
RISE AND FALL TIME NS (10%-90%)
18 16 14 12 10
SCK (66 MHZ DRIVER), EVDDMIN = 2.25V, TEMPERATURE = 85C
25
RISE TIME
20
RISE TIME
15 FALL TIME 10
FALL TIME 8 6 4 2
5
0 0
50
100 150 LOAD CAPACITANCE (PF)
200
250
0
0
50
100 150 LOAD CAPACITANCE (PF)
200
250
Figure 40. Typical Output Delay or Hold for Driver C at EVDDMIN
Figure 42. Typical Output Delay or Hold for Driver D at EVDDMIN
20 RISE AND FALL TIME NS (10%-90%) 18 16
TMR0 (33 MHZ DRIVER), EVDDMAX = 3.65V, TEMPERATURE = 85C
RISE AND FALL TIME NS (10%-90%)
14
SCK (66 MHZ DRIVER), EVDDMAX = 3.65V, TEMPERATURE = 85C
12 10
RISE TIME
14 12 FALL TIME 10 8 6 4 2 0
RISE TIME
8 FALL TIME 6 4 2
0
50
100 150 LOAD CAPACITANCE (PF)
200
250
0
0
50
100 150 LOAD CAPACITANCE (PF)
200
250
Figure 41. Typical Output Delay or Hold for Driver C at EVDDMAX
Figure 43. Typical Output Delay or Hold for Driver D at EVDDMAX
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ADSP-BF531/ADSP-BF532/ADSP-BF533
ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application printed circuit board use: T J = T CASE + ( JT x P D ) where: TJ = Junction temperature ( C) TCASE = Case temperature ( C) measured by customer at top center of package. JT = From Table 33 PD = Power dissipation (see Power Dissipation on Page 41 for the method to calculate PD) Values of JA are provided for package comparison and printed circuit board design considerations. JA can be used for a first order approximation of TJ by the equation: T J = T A + ( JA x P D ) where: TA = Ambient temperature ( C) In Table 33, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board measurement complies with JESD51-8. The junction-to-case measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board. Thermal resistance JA in Table 33 is the figure of merit relating to performance of the package and board in a convective environment. JMA represents the thermal resistance under two conditions of airflow. JB represents the heat extracted from the periphery of the board. JT represents the correlation between TJ and TCASE. Values of JB are provided for package comparison and printed circuit board design considerations. Table 33. Thermal Characteristics for BC-160 Package
Parameter JA JMA JMA JB JC JT Condition 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow Not applicable Not applicable 0 Linear m/s Airflow Typical 34.1 30.1 28.8 25.55 8.75 0.13 Unit C/W C/W C/W C/W C/W C/W
Table 35. Thermal Characteristics for B-169 Package
Parameter JA JMA JMA JB JC JT Condition 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow Not applicable Not applicable 0 Linear m/s Airflow Typical 28.6 24.6 23.8 21.75 12.7 0.78 Unit C/W C/W C/W C/W C/W C/W
Table 34. Thermal Characteristics for ST-176-1 Package
Parameter JA JMA JMA JT JT JT Condition 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow Typical 34.9 33.0 32.0 0.50 0.75 1.00 Unit C/W C/W C/W C/W C/W C/W
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ADSP-BF531/ADSP-BF532/ADSP-BF533
160-LEAD BGA PINOUT
Table 36 lists the BGA pinout by signal. Table 37 on Page 47 lists the BGA pinout by ball number. Table 36. 160-Ball BGA Pin Assignment (Alphabetically by Signal)
Signal ABE0 ABE1 ADDR1 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 BR CLKIN CLKOUT DATA0 DATA1 DATA10 DATA11 Ball No. H13 H12 J14 M13 M14 N14 N13 N12 M11 N11 P13 P12 P11 K14 L14 J13 K13 L13 K12 L12 M12 E14 F14 F13 G12 G13 E13 G14 H14 P10 N10 N4 P3 D14 A12 B14 M9 N9 N6 P6 Signal DATA12 DATA13 DATA14 DATA15 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DR0PRI DR0SEC DR1PRI DR1SEC DT0PRI DT0SEC DT1PRI DT1SEC EMU GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. M5 N5 P5 P4 P9 M8 N8 P8 M7 N7 P7 M6 K1 J2 G3 F3 H1 H2 F2 E3 M2 A10 A14 B11 C4 C5 C11 D4 D7 D8 D10 D11 F4 F11 G11 H4 H11 K4 K11 L5 Signal GND GND GND GND GND GND MISO MOSI NMI PF0 PF1 PF10 PF11 PF12 PF13 PF14 PF15 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PPI0 PPI1 PPI2 PPI3 PPI_CLK RESET RFS0 RFS1 RSCLK0 RSCLK1 RTXI RTXO RX SA10 SCAS Ball No. L6 L8 L10 M4 M10 P14 E2 D3 B10 D2 C1 A4 A5 B5 B6 A6 C6 C2 C3 B1 B2 B3 B4 A2 A3 C8 B8 A7 B7 C9 C10 J3 G2 L1 G1 A9 A8 L3 E12 C14 Signal SCK SCKE SMS SRAS SWE TCK TDI TDO TFS0 TFS1 TMR0 TMR1 TMR2 TMS TRST TSCLK0 TSCLK1 TX VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDRTC VROUT0 VROUT1 XTAL Ball No. D1 B13 C13 D13 D12 P2 M3 N3 H3 E1 L2 M1 K2 N2 N1 J1 F1 K3 A1 C7 C12 D5 D9 F12 G4 J4 J12 L7 L11 P1 D6 E4 E11 J11 L4 L9 B9 A13 B12 A11
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 37 lists the BGA pinout by ball number. Table 36 on Page 46 lists the BGA pinout by signal. Table 37. 160-Ball BGA Pin Assignment (Numerically by Ball Number)
Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 Signal VDDEXT PF8 PF9 PF10 PF11 PF14 PPI2 RTXO RTXI GND XTAL CLKIN VROUT0 GND PF4 PF5 PF6 PF7 PF12 PF13 PPI3 PPI1 VDDRTC NMI GND VROUT1 SCKE CLKOUT PF1 PF2 PF3 GND GND PF15 VDDEXT PPI0 PPI_CLK RESET GND VDDEXT Ball No. C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E11 E12 E13 E14 F1 F2 F3 F4 F11 F12 F13 F14 G1 G2 G3 G4 G11 G12 G13 G14 Signal SMS SCAS SCK PF0 MOSI GND VDDEXT VDDINT GND GND VDDEXT GND GND SWE SRAS BR TFS1 MISO DT1SEC VDDINT VDDINT SA10 ARDY AMS0 TSCLK1 DT1PRI DR1SEC GND GND VDDEXT AMS2 AMS1 RSCLK1 RFS1 DR1PRI VDDEXT GND AMS3 AOE ARE Ball No. H1 H2 H3 H4 H11 H12 H13 H14 J1 J2 J3 J4 J11 J12 J13 J14 K1 K2 K3 K4 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 Signal DT0PRI DT0SEC TFS0 GND GND ABE1 ABE0 AWE TSCLK0 DR0SEC RFS0 VDDEXT VDDINT VDDEXT ADDR4 ADDR1 DR0PRI TMR2 TX GND GND ADDR7 ADDR5 ADDR2 RSCLK0 TMR0 RX VDDINT GND GND VDDEXT GND VDDINT GND VDDEXT ADDR8 ADDR6 ADDR3 TMR1 EMU Ball No. M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Signal TDI GND DATA12 DATA9 DATA6 DATA3 DATA0 GND ADDR15 ADDR9 ADDR10 ADDR11 TRST TMS TDO BMODE0 DATA13 DATA10 DATA7 DATA4 DATA1 BGH ADDR16 ADDR14 ADDR13 ADDR12 VDDEXT TCK BMODE1 DATA15 DATA14 DATA11 DATA8 DATA5 DATA2 BG ADDR19 ADDR18 ADDR17 GND
Figure 44 lists the top view of the BGA ball configuration. Figure 45 lists the bottom view of the BGA ball configuration.
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ADSP-BF531/ADSP-BF532/ADSP-BF533
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A B C D E F G H J K L M N P
KEY: VDDINT VDDEXT
GND
VDDRTC VROUT
I/O
Figure 44. 160-Ball BGA Ball Configuration (Top View)
14 13 12 11 10 9 8 7 6 5 4 3 2 1
A B C D E F G H J K L M N P
KEY: VDDINT VDDEXT
GND
VDDRTC VROUT
I/O
Figure 45. 160-Ball BGA Ball Configuration (Bottom View)
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ADSP-BF531/ADSP-BF532/ADSP-BF533
169-BALL PBGA PINOUT
Table 38 lists the PBGA pinout by signal. Table 39 on Page 52 lists the PBGA pinout by ball number. Table 38. 169-Ball PBGA Pin Assignment (Alphabetically by Signal)
Signal ABE [0] ABE [1] ADDR [1] ADDR [10] ADDR [11] ADDR [12] ADDR [13] ADDR [14] ADDR [15] ADDR [16] ADDR [17] ADDR [18] ADDR [19] ADDR [2] ADDR [3] ADDR [4] ADDR [5] ADDR [6] ADDR [7] ADDR [8] ADDR [9] AMS [0] AMS [1] AMS [2] AMS [3] AOE ARDY ARE AWE BG BGH BMODE [0] BMODE [1] BR CLKIN CLKOUT DATA [0] DATA [1] DATA [10] DATA [11] Ball No. H16 H17 J16 N16 P17 P16 R17 R16 T17 U15 T15 U16 T14 J17 K16 K17 L16 L17 M16 M17 N17 D17 E16 E17 F16 F17 C16 G16 G17 T13 U17 U5 T5 C17 A14 D16 U14 T12 T8 U8 Signal DATA [13] DATA [14] DATA [15] DATA [2] DATA [3] DATA [4] DATA [5] DATA [6] DATA [7] DATA [8] DATA [9] DR0PRI DR0SEC DR1PRI DR1SEC DT0PRI DT0SEC DT1PRI DT1SEC EMU EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD GND GND GND GND GND GND Ball No. T7 U6 T6 U13 T11 U12 U11 T10 U10 T9 U9 M2 M1 H1 H2 K2 K1 F1 F2 U1 B2 F6 F7 F8 F9 G6 H6 J6 K6 L6 M6 M7 M8 T2 B16 F11 G7 G8 G9 G10 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND MISO MOSI NMI PF [0] PF [1] PF [10] PF [11] PF [12] PF [13] PF [14] PF [15] PF [2] PF [3] PF [4] PF [5] PF [6] PF [7] Ball No. G11 H7 H8 H9 H10 H11 J7 J8 J9 J10 J11 K7 K8 K9 K10 K11 L7 L8 L9 L10 L11 M9 T16 E2 E1 B11 D2 C1 B5 A5 A6 B6 A7 B7 B1 C2 A1 A2 B3 A3 Signal PF [8] PF [9] PPI [0] PPI [1] PPI [2] PPI [3] PPI_CLK RESET RFS0 RFS1 RSCLK0 RSCLK1 RTCVDD RTXI RTXO RX SA10 SCAS SCK SCKE SMS SRAS SWE TCK TDI TDO TFS0 TFS1 TMR0 TMR1 TMR2 TMS TRST TSCLK0 TSCLK1 TX VDD VDD VDD VDD Ball No. B4 A4 B9 A9 B8 A8 B10 A12 N1 J1 N2 J2 F10 A10 A11 T1 B15 A16 D1 B14 A17 A15 B17 U4 U3 T4 L1 G2 R1 P2 P1 T3 U2 L2 G1 R2 F12 G12 H12 J12 Signal VDD VDD VDD VDD VDD VROUT VROUT XTAL Ball No. K12 L12 M10 M11 M12 B12 B13 A13
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 39 lists the PBGA pinout by ball number. Table 38 on Page 51 lists the PBGA pinout by signal. Table 39. 169-Ball PBGA Pin Assignment (Numerically by Ball Number)
Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C16 C17 D1 D2 Signal PF [4] PF [5] PF [7] PF [9] PF [11] PF [12] PF [14] PPI [3] PPI [1] RTXI RTXO RESET XTAL CLKIN SRAS SCAS SMS PF [2] EVDD PF [6] PF [8] PF [10] PF [13] PF [15] PPI [2] PPI [0] PPI_CLK NMI VROUT VROUT SCKE SA10 GND SWE PF [1] PF [3] ARDY BR SCK PF [0] Ball No. D16 D17 E1 E2 E16 E17 F1 F2 F6 F7 F8 F9 F10 F11 F12 F16 F17 G1 G2 G6 G7 G8 G9 G10 G11 G12 G16 G17 H1 H2 H6 H7 H8 H9 H10 H11 H12 H16 H17 J1 Signal CLKOUT AMS [0] MOSI MISO AMS [1] AMS [2] DT1PRI DT1SEC EVDD EVDD EVDD EVDD RTCVDD GND VDD AMS [3] AOE TSCLK1 TFS1 EVDD GND GND GND GND GND VDD ARE AWE DR1PRI DR1SEC EVDD GND GND GND GND GND VDD ABE [0] ABE [1] RFS1 Ball No. J2 J6 J7 J8 J9 J10 J11 J12 J16 J17 K1 K2 K6 K7 K8 K9 K10 K11 K12 K16 K17 L1 L2 L6 L7 L8 L9 L10 L11 L12 L16 L17 M1 M2 M6 M7 M8 M9 M10 M11 Signal RSCLK1 EVDD GND GND GND GND GND VDD ADDR [1] ADDR [2] DT0SEC DT0PRI EVDD GND GND GND GND GND VDD ADDR [3] ADDR [4] TFS0 TSCLK0 EVDD GND GND GND GND GND VDD ADDR [5] ADDR [6] DR0SEC DR0PRI EVDD EVDD EVDD GND VDD VDD Ball No. M12 M16 M17 N1 N2 N16 N17 P1 P2 P16 P17 R1 R2 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 Signal VDD ADDR [7] ADDR [8] RFS0 RSCLK0 ADDR [10] ADDR [9] TMR2 TMR1 ADDR [12] ADDR [11] TMR0 TX ADDR [14] ADDR [13] RX EVDD TMS TDO BMODE [1] DATA [15] DATA [13] DATA [10] DATA [8] DATA [6] DATA [3] DATA [1] BG ADDR [19] ADDR [17] GND ADDR [15] EMU TRST TDI TCK BMODE [0] DATA [14] DATA [12] DATA [11] Ball No. U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal DATA [11] DATA [9] DATA [7] DATA [5] DATA [4] DATA [2] DATA [0] ADDR [16] ADDR [18] BGH
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ADSP-BF531/ADSP-BF532/ADSP-BF533
176-LEAD LQFP PINOUT
Table 40 lists the LQFP pinout by signal. Table 41 on Page 52 lists the LQFP pinout by lead number. Table 40. 176-Lead LQFP Pin Assignment (Alphabetically by Signal)
Signal ABE0 ABE1 ADDR1 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 BR CLKIN CLKOUT DATA0 DATA1 DATA10 Lead No. 151 150 149 137 136 135 127 126 125 124 123 122 121 148 147 146 142 141 140 139 138 161 160 159 158 154 162 153 152 119 120 96 95 163 10 169 116 115 103 Signal DATA11 DATA12 DATA13 DATA14 DATA15 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DR0PRI DR0SEC DR1PRI DR1SEC DT0PRI DT0SEC DT1PRI DT1SEC EMU GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Lead No. 102 101 100 99 98 114 113 112 110 109 108 105 104 74 73 63 62 68 67 59 58 83 1 2 3 7 8 9 15 19 30 39 40 41 42 43 44 56 70 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND MISO MOSI NMI PF0 PF1 PF10 PF11 PF12 PF13 PF14 PF15 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 Lead No. 88 89 90 91 92 97 106 117 128 129 130 131 132 133 144 155 170 174 175 176 54 55 14 51 50 34 33 32 29 28 27 49 48 47 46 38 37 36 35 Signal PPI_CLK PPI0 PPI1 PPI2 PPI3 RESET RFS0 RFS1 RSCLK0 RSCLK1 RTXI RTXO RX SA10 SCAS SCK SCKE SMS SRAS SWE TCK TDI TDO TFS0 TFS1 TMR0 TMR1 TMR2 TMS TRST TSCLK0 TSCLK1 TX VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Lead No. 21 22 23 24 26 13 75 64 76 65 17 16 82 164 166 53 173 172 167 165 94 86 87 69 60 79 78 77 85 84 72 61 81 6 12 20 31 45 57 Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDRTC VROUT1 VROUT2 XTAL Lead No. 71 93 107 118 134 145 156 171 25 52 66 80 111 143 157 168 18 5 4 11
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 41 lists the LQFP pinout by lead number. Table 40 on Page 51 lists the LQFP pinout by signal. Table 41. 176-Lead LQFP Pin Assignment (Numerically by Lead Number)
Lead No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal GND GND GND VROUT2 VROUT1 VDDEXT GND GND GND CLKIN XTAL VDDEXT RESET NMI GND RTXO RTXI VDDRTC GND VDDEXT PPI_CLK PPI0 PPI1 PPI2 VDDINT PPI3 PF15 PF14 PF13 GND VDDEXT PF12 PF11 PF10 PF9 PF8 PF7 PF6 GND GND Lead No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Signal GND GND GND GND VDDEXT PF5 PF4 PF3 PF2 PF1 PF0 VDDINT SCK MISO MOSI GND VDDEXT DT1SEC DT1PRI TFS1 TSCLK1 DR1SEC DR1PRI RFS1 RSCLK1 VDDINT DT0SEC DT0PRI TFS0 GND VDDEXT TSCLK0 DR0SEC DR0PRI RFS0 RSCLK0 TMR2 TMR1 TMR0 VDDINT Lead No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Signal TX RX EMU TRST TMS TDI TDO GND GND GND GND GND VDDEXT TCK BMODE1 BMODE0 GND DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 GND VDDEXT DATA7 DATA6 DATA5 VDDINT DATA4 DATA3 DATA2 DATA1 DATA0 GND VDDEXT BG BGH Lead No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Signal ADDR19 ADDR18 ADDR17 ADDR16 ADDR15 ADDR14 ADDR13 GND GND GND GND GND GND VDDEXT ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 VDDINT GND VDDEXT ADDR4 ADDR3 ADDR2 ADDR1 ABE1 ABE0 AWE ARE AOE GND VDDEXT VDDINT AMS3 AMS2 AMS1 Lead No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Signal AMS0 ARDY BR SA10 SWE SCAS SRAS VDDINT CLKOUT GND VDDEXT SMS SCKE GND GND GND
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ADSP-BF531/ADSP-BF532/ADSP-BF533
OUTLINE DIMENSIONS
Dimensions in Figure 46--160-Ball Plastic Ball Grid Array, mini-BGA (BC-160), Figure 47--176-LEAD LQFP (ST-176-1) and Figure 48--169-Ball Plastic Ball Grid Array, mini-BGA (B-169) are shown in millimeters.
12.00 BSC SQ
14 12 10 8 64 2 13 11 9 7 5 31
A1 CORNER INDEX AREA
A B C D E F G H J K L M N P
BALL A1 INDICATOR 10.40 BSC SQ
TOP VIEW
0.80 BSC BALL PITCH 1.31 1.21 1.11 BOTTOM VIEW
1.70 MAX
DETAIL A
SEATING PLANE 0.40 NOM (NOTE 3) NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-205, VARIATION AE. 3. MINIMUM BALL HEIGHT 0.25.
0.12 0.55 MAX 0.50 COPLANARITY 0.45 BALL DIAMETER
DETAIL A
Figure 46. 160-Ball Plastic Ball Grid Array, mini-BGA (BC-160)
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ADSP-BF531/ADSP-BF532/ADSP-BF533
26.00 BSC SQ 24.00 BSC SQ 176 1 0.27 0.22 0.17 133 132
0.75 0.60 0.45 PIN 1
SEATING PLANE 0.08 MAX LEAD COPLANARITY 0.15 0.05
1.45 1.40 1.35 1.60 MAX DETAIL A
44 45 DETAIL A 0.50 BSC LEAD PITCH TOP VIEW (PINS DOWN)
89 88
NOTES 1. DIMENSIONS IN MILLIMETERS 2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION. 3. CENTER DIMENSIONS ARE NOMINAL
Figure 47. 176-LEAD LQFP (ST-176-1)
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ADSP-BF531/ADSP-BF532/ADSP-BF533
BOTTOM VIEW A1 BALL PAD CORNER
19.00 BSC SQ 16.00 BSC SQ 1.00 BSC BALL PITCH A B C D E F G H J K L M N P R T U 16 14 12 10 8 6 4 2 17 15 13 11 9 7 5 3 1
TOP VIEW
0.40 MIN
2.50 2.23 1.97
SIDE VIEW DETAIL A 0.20 MAX COPLANARITY SEATING PLANE DETAIL A
NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MS-034, VARIATION AAG-2 . 3. MINIMUM BALL HEIGHT 0.40
0.70 BALL DIAMETER 0.60 0.50
Figure 48. 169-Ball Plastic Ball Grid Array, mini-BGA (B-169)
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ADSP-BF531/ADSP-BF532/ADSP-BF533
ORDERING GUIDE
Part Number Temperature Range (Ambient ) 0C to 70C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C Package Description Instruction Operating Voltage Rate (Max) 600 MHz 500 MHz 500 MHz 400 MHz 400 MHz 400 MHz 400 MHz 400 MHz 400 MHz 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O
ADSP-BF533SKBC600 ADSP-BF533SBBC500 ADSP-BF533SBBZ5001 ADSP-BF532SBBC400 ADSP-BF532SBST400 ADSP-BF532SBBZ4001 ADSP-BF531SBBC400 ADSP-BF531SBST400 ADSP-BF531SBBZ4001
1
Chip Scale Package Ball Grid Array (mini-BGA) BC-160 Chip Scale Package Ball Grid Array (mini-BGA) BC-160 Plastic Ball Grid Array (PBGA) B-169 Chip Scale Package Ball Grid Array (mini-BGA) BC-160 Quad Flatpack (LQFP) ST-176-1 Plastic Ball Grid Array (PBGA) B-169 Chip Scale Package Ball Grid Array (mini-BGA) BC-160 Quad Flatpack (LQFP) ST-176-1 Plastic Ball Grid Array (PBGA) B-169
Z = Pb-free part.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03728-0-3/04(0)
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